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[edit] Overview

Netmaker is a library of fully-synthesizable parameterized Network-on-Chip (NoC) implementations. These networks are designed to provide packet-based communication for complex multi-processor SoCs and multi/many-core processors.

The aim of the library is to aid the accurate characterisation of potential router microarchitectures, routing algorithms and network topologies. The ability to synthesize gate-level implementations also allows the library to be used when exploiting FPGA-based environments for manycore research (e.g. RAMP, Protoflex) or when producing prototypes. These implementations will also hopefully prove useful when evaluating new router/network architectures.

[edit] Features

  • Library can create a wide-range of routers and networks
  • Credit-based flow-control on links, support for pipelined links or arbitrary link latencies
  • Wide range of parameters supported through simple configuration files
  • Automatic sweeping of parameters
  • Library is written in SystemVerilog (supporting both simulation and synthesis)

[edit] Getting Started

Netmaker Documentation is at an early stage but will be expanded soon.

If you are thinking about extending the library to implement a particular topology or router please check the list of ongoing projects and planned work. I would of course be very interested to hear about your plans and may be able to offer some assistance.

The latest version of Netmaker (Beta 0.82 - April, 2009)

Version History

[edit] Contact Details

My Computer Laboratory web page

Robert Mullins

[edit] Licensing

Netmaker is distributed under the conditions of the GNU General Public License (GPL). If your requirements are incompatible with the GNU GPL please contact me.

Netmaker is provided without a warranty of any kind and no guarantees are provided regarding its correctness or fitness for a particular purpose.

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